Design and implementation of low-cost hardware architecture for authentication encryption algorithm SM4-GCM

Rui CHEN; Chunqiang LI

doi:10.11959/j.issn.2096-3750.2023.00362

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Design and implementation of low-cost hardware architecture for authentication encryption algorithm SM4-GCM

Theory and Technology | 更新时间：2024-08-16

- Design and implementation of low-cost hardware architecture for authentication encryption algorithm SM4-GCM
- Chinese Journal on Internet of Things Vol. 7, Issue 4, Pages: 168-179(2023)
- 作者机构：
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- DOI：10.11959/j.issn.2096-3750.2023.00362
  CLC： TN918.4
- Online First：2023-12，
  
  Published：20 December 2023
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Rui CHEN, Chunqiang LI. Design and implementation of low-cost hardware architecture for authentication encryption algorithm SM4-GCM[J]. Chinese Journal on Internet of Things, 2023, 7(4): 168-179.
DOI：

Rui CHEN, Chunqiang LI. Design and implementation of low-cost hardware architecture for authentication encryption algorithm SM4-GCM[J]. Chinese Journal on Internet of Things, 2023, 7(4): 168-179. DOI： 10.11959/j.issn.2096-3750.2023.00362.

摘要

物联网已被广泛应用于各行各业，该项技术的赋能使得行业应用更好地向数字化、智能化方向发展。在一些行业应用中，物联网设备采集的数据与用户隐私和财产安全关系密切。为了保护数据安全，基于国产认证加密算法SM4-GCM（Galois/Counter Mode），提出一种低成本、多功能的硬件架构设计。设计兼顾性能、成本和硬件级的数据机密性和完整性保障，同时也支持3种工作模式：SM4-CTR、SM4-ECB和SM4-GCM。在现场可编程门阵列（FPGA

field programmable gate array）开发板上的实现结果显示，该设计仅需1 761个查找表和1 825个寄存器，占用的资源片仅为604，而吞吐率达到39.78 Mbit/s@100 MHz，能够满足物联网数据安全应用需求。

Abstract

The internet of things (IoT) has gained wide adoption across various industries

driving digitalization and intelligence in industry applications.However

the data collected by IoT devices in some industry applications may be closely linked to user privacy and property security.To ensure the security of such data

a cost-effective

multifunctional hardware architecture design based on the Chinese authenticated encryption algorithm SM4-GCM (Galois/Counter Mode) was proposed

which offered a balanced approach to performance

cost

and hardware-level data confidentiality and integrity assurance

and supported three operation modes: SM4-CTR

SM4-ECB

and SM4-GCM.The implementation results on the field programmable gate array (FPGA) development board demonstrate that the design requires only 1 761 look-up tables and 1 825 registers

occupies only 604 slices

and has a throughput rate of 39.78 Mbit/s@100 MHz.These results suggest that the proposed design can effectively meet the requirements of IoT data security applications.

关键词

Keywords

references

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