工业物联网中的缓冲内存管理设计与实现

吴超; 王成群; 朱升宏; 徐伟强; 贾宇波

doi:10.11959/j.issn.2096-3750.2019.00088

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工业物联网中的缓冲内存管理设计与实现

理论与技术 | 更新时间：2024-06-05

- 工业物联网中的缓冲内存管理设计与实现
- Design and implementation of buffer memory management in industrial Internet of things
- 物联网学报 2019年3卷第1期页码：60-64
- 作者机构：
  
  1. 浙江理工大学信息学院，浙江杭州 310000
  2. 新华三技术有限公司，浙江杭州 310000
- 作者简介：
  
  [ "吴超（1994- ），男，江苏盐城人，浙江理工大学硕士生，主要研究方向为物联网、工业互联网等。" ]
  [ "王成群（1981- ），男，湖北宜昌人，博士，浙江理工大学讲师，主要研究方向为工业互联网、AI及其在行业中的应用等。" ]
  [ "朱升宏（1968- ），男，浙江杭州人，高级工程师，新华三技术有限公司副总裁，主要研究方向为无线网络、人工智能、信号与信息处理等。" ]
  [ "徐伟强（1975- ）男，浙江杭州人，博士，浙江理工大学教授、硕士生导师，主要研究方向为工业互联网、物联网、网络与智能等。" ]
  [ "贾宇波（1964- ）男，浙江绍兴人，浙江理工大学教授、硕士生导师，主要研究方向为 Web 挖掘技术研究、软件开发方法研究、网络通信协议研究等。" ]
- 基金信息：
  
  浙江省重点研发计划资助项目;The Key Research and Development Program Foundation of Zhejiang(2018C01093)
- DOI：10.11959/j.issn.2096-3750.2019.00088
  中图分类号： TP393
- 纸质出版日期：2019-03-30，
  
  网络出版日期：2019-03，
- 稿件说明：
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吴超, 王成群, 朱升宏, 等. 工业物联网中的缓冲内存管理设计与实现[J]. 物联网学报, 2019,3(1):60-64.

CHAO WU, CHENGQUN WANG, SHENGHONG ZHU, et al. Design and implementation of buffer memory management in industrial Internet of things. [J]. Chinese journal on internet of things, 2019, 3(1): 60-64.
吴超, 王成群, 朱升宏, 等. 工业物联网中的缓冲内存管理设计与实现[J]. 物联网学报, 2019,3(1):60-64. DOI： 10.11959/j.issn.2096-3750.2019.00088.

CHAO WU, CHENGQUN WANG, SHENGHONG ZHU, et al. Design and implementation of buffer memory management in industrial Internet of things. [J]. Chinese journal on internet of things, 2019, 3(1): 60-64. DOI： 10.11959/j.issn.2096-3750.2019.00088.

摘要

针对工业物联网高速通信中出现流量堵塞如何高效存储的问题，引入了内存管理的方法。在研究同步动态随机存储器（SDRAM）存储原理的基础上，设计了一种基于现场可编程逻辑门阵列（FPGA）的SDRAM分区内存管理系统。采用FPGA作为主控制器，将SDRAM分成索引区和数据区两部分，为了方便内存管理，进一步将SDRAM数据区分成若干个1 kB大小相同的内存块，实现通过索引读写数据的目的。仿真结果表明，该内存管理系统配合FIFO（first input first output）的使用，可以有效解决在高速通信中出现流量堵塞后从SDRAM中读取多条数据帧造成数据错乱等不可靠问题，提高了通信系统的稳定性。

Abstract

Aiming at the problem of how to store traffic jam efficiently in high-speed communication of industrial Internet of things

the method of memory management was introduced.On the basis of researching the storage principle of SDRAM

a SDRAM partition memory management system based on field programmable gate array (FPGA) was designed.FPGA was used as the main controller

SDRAM was divided into two parts:index area and data area.In order to facilitate memory management

SDRAM data was further divided into memory blocks with the same size of 1 kB to achieve the purpose of reading and writing data through index.The simulation and experimental results show that the unreliable problems such as data disorder caused by reading multiple data frames from SDRAM after traffic congestion in high-speed communication can be solved effectively

and the stability of communication system can be improved by the memory management system combined with FIFO.

关键词

工业物联网现场可编程逻辑门阵列同步动态随机存储器内存管理

Keywords

industrial Internet of thingsfield programmable gate arraysynchronous dynamic random access memorymemory management

references

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